This invention relates generally to semiconductor structures and manufacturing methods, and more particularly to structures and methods having reduced electrical short circuits between adjacent electrical contacts to the semiconductor.
As is known in the art, as dimensions between adjacent devices in a semiconductor body become smaller and smaller, the probability of electrical shorts between adjacent contacts increases. For example, borderless bitline contacts in Dynamic Random Access Memory (DRAM) arrays suffer from extensive and uncontrolled enlargement surrounding the pre-metal dielectric because of a wet clean performed prior to polycrystalline (poly) silicon deposition. More particularly, referring to FIGS. 1, 2A and 3A, a DRAM array 9 is shown at an early stage in the fabrication thereof. The array 9 is formed in a semiconductor body 10, here single crystal silicon. Here the array includes trench capacitors C as the storage elements. Each storage capacitor C is electrically connected to the drain D region of a CMOS transistor T associated with one of the DRAM cells in the array 9. The transistors T are formed in rows of active areas 11. The rows of active areas are electrically isolated from each other by shallow trench isolation (STI) regions 13. The array includes columns of wordline WL which are provide gate electrodes for the transistors T. Here a pair of adjacent transistors T in each one of the rows share a common source region S. The common source regions S are to be connected to bitlines of the DRAM array. As noted in FIG. 2A, gate electrode stack 15 of two adjacent transistors T in a common row thereof, are formed on a thermally grown gate oxide layer 12, it being understood that dimensions in the FIGS. are not to scale.
Thus, the array of DRAM cells includes a plurality of transistors T disposed in rows of electrically isolated active areas 11 of a surface of a semiconductor body 10. The transistors T have gate stacks 18 disposed in columns across the rows of active areas 11 and source/drain regions, here source regions S, it being understood that the terms source and drain may be used interchangeably, in the regions of the active areas 11 between adjacent pairs of the columns of gate stacks 18. It is also noted that the gate oxide layer 12 is disposed over the entire surface of the silicon body 10. Thus, there are portions of the gate oxide layer 12 on the portions of the active regions 11 under the columns of gate stacks 18 (FIGS. 1 and 2A) as well as on portions of the active regions 11 between the columns of gate stacks 18 (FIGS. 1 and 3A). Here, the gate electrode stack 15 includes a bottom layer 14 of doped polycrystalline silicon, a middle layer 16 of tungsten silicide, and a cap 18 of silicon nitride, as well as silicon nitride sidewall spacers 20.
Referring now to FIGS. 2B and 3B, a layer 32 of silicon nitride is formed over the surface of the structure shown in FIGS. 1, 2A and 3A. Next, a pre-metal dielectric layer 34, typically borophosphosilicate glass (BPSG), is deposited, thermally reflowed to fill any gaps, and planarized using chemical mechanical polishing (CMP) to produce the structure shown. It should be understood that, for the BPSG top surface may, or may not, be aligned to the top of the cap 18 of silicon nitride afterwards. Further, in order to improve the reflow, the BPSG has a relatively high amount of boron to accommodate the reflow-temperature requirements of small geometry devices. In any event, a film 36 of doped or undoped silicon oxide is finally deposited as a blanket layer to tune the distance to the next level of metalization. To manufacture a "self-aligned" contact to the source regions, outlined by dotted lines 37 in FIG. 1, a photoresist mask 38 is applied and patterned with windows 39, as shown in FIGS. 2B and 3B. It is noted that the width W of the windows 39 are slightly wider than the gap between the gate electrode stacks 15 (FIG. 2B). The portions of the oxide film 36, BPSG layer 34 stack exposed by the windows 39 are etched with a dry etch (e.g., anisotropic RIE) which removes silicon dioxide in film 36 and BPSG in layer 34 at a substantially higher etch rate than the etch rate of the photoresist mask 38 or the silicon nitride 32. Thus, the etch stops at the silicon nitride layer 32, as indicated in FIG. 2C, 3C. The resulting structure, after the mask 38 is removed, is shown in FIGS. 2C and 3C. It is noted that the contact openings, or vias 41 formed by the etching process are self aligned along the rows of active regions 11 (FIG. 1), as shown in FIG. 2C because of the silicon nitride 32; however, the openings 41 are not self-aligned in the orthogonal direction (i.e., a direction parallel to the columns of wordlines to be formed, as indicated in FIG. 3C.
Next, the photoresist mask 38 is stripped, the silicon nitride layer 32 is etched away, with the much thicker silicon nitride spacers 20 being slightly eroded, to produce the structure shown in FIGS. 2D and 3D. To complete the electrical contact to the source regions S, the portions of the gate oxide 12 between the gate electrode stacks 14, must be removed. Typically, a dilute hydrofluoric acid (HF) etch dip is used to: (1) remove any residual material which may remain from the dry etch; and (2) to ensure that the silicon dioxide layer between the gate electrode stacks 14 is totally removed (i.e., the silicon 10 is exposed). The HF etch etches silicon dioxide at a greater etch rate than silicon nitride. The resulting structure is shown in FIGS. 2E and 3E. It is noted that while the silicon nitride spacers provide protection to the gate electrode stacks 14 during the dilute hydrofluoric acid dip, the dip eats into (i.e., etches-out) the portions of the BPSG layer 14 and silicon dioxide 36 along the perpendicular direction (i.e., the direction parallel to the columns of wordlines) because there is no silicon nitride spacers, as indicated in FIGS. 3D and 3E. This etch-out of the BPSG is increased as the amount of boron in the BPSG is increases to accommodate the reflow-temperature requirements of small geometry devices. Thus, the width W' of the BPSG layer 34 and silicon dioxide is significantly reduced.
Next, a layer 40 of conductive material 40 is applied to the surface of the structures shown in FIGS. 2E and 3E and then planarized to produce the bitline contacts to the source regions S (FIG. 2F). It is noted, however, in FIG. 3F, that the reduction in the width W' (FIG. 3E) increases the probably of an electrical short between adjacent bitlines, BLs, as shown in FIG. 3F.
As is also known in the art, if the conductive material 40 is doped polycrystalline silicon (i.e., poly), there is no need for implantation provided dopant in the silicon 10, i.e., with doped poly, there is no need for dopant in the silicon to provide an ohmic contact between the doped poly and the silicon. If the conductive material 40 is a metal, however, dopant is required in the silicon 10 in order to achieve ohmic contact. Using ion implantation to provide these doped regions, however, requires a thermal anneal step to activate the implanted ions. The thermal anneal also, however, diffuses the dopant which may have an adverse effect on device characteristics with small devices. Also, polycrystalline silicon fills high aspect rations very well; however, it has a disadvantage over metal because of the relatively high resistance of doped poly compared to that of metal.